View MB89P657APFV-102_2101480.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-12530-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89650ar series mb89653ar/655ar/656ar/657ar/p657a mb89pv650a n description the mb89650ar series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, pwm timers, a serial interface, an a/d converter, external interrupts, an lcd controller/driver, and a watch prescaler. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-8l family cpu core ? dual-clock control system ? maximum memory space: 64 kbytes ? minimum execution time: 0.4 m s/10 mhz ? interrupt processing time: 3.6 m s/10 mhz ? i/o ports: max. 64 channels ? 21-bit time-base counter ? 8-bit pwm timers: 2 channels (a maximum of 4 channels can be used for output.) ? 8/16-bit timer/counter: 4 channels (16 bits 2 channels) ? 8-bit serial i/o: 1 channel ? 8-bit a/d converter: 8 channels (continued) n pac k ag e (fpt-100p-m05) (mqp-100c-p02) (fpt-100p-m06) 100-pin plastic sqfp 100-pin plastic qfp 100-pin ceramic mqfp
2 mb89650ar series (continued) ? external interrupt 1 four independent channels with edge detection function ? external interrupt 2 (wake-up function) twelve l level-interrupt channels ? watch prescaler ? lcd controller/driver: 16 to 32 segments 2 to 4 commons ? power-on reset function ? low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) ? sqfp-100 and qfp-100 packages n product lineup (continued) mb89655ar mb89656ar mb89657ar mb89p657a mb89pv650a classification mass production products (mask rom products) one-time prom product piggyback/ evaluation product (for evaluation and development) rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 24 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) 32 k 8 bits (internal prom, programming with general- purpose eprom programmer) 32 k 8 bits (external rom) ram size 256 8 bits 512 8 bits 768 8 bits 1 k 8 bits lcd display ram 16 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz to 6.4 m s/10 mhz, 61.0 m s/32.768 khz interrupt processing time: 3.6 m s/10 mhz to 57.6 m s/10 mhz, 549.3 m s/32.768 khz ports input ports: 8 (all also serve as peripherals.) output ports: 8 (all also serve as peripherals.) i/o ports: 48 (all also serve as peripherals.) to t a l : 6 4 8-bit timer 1, 8-bit timer 2 8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 m s) 16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 m s) 2 output channels are enabled when operating as an 8-bit timer. 8-bit timer 3, 8-bit timer 4 8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 m s) 16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 m s) 2 output channels are enabled when operating as an 8-bit timer. clock timer 21 bits 1 (in main clock mode)/15 bits 1 (at 32.768 khz) 8-bit pwm timer 1, 8-bit pwm timer 2 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s to 3.3 ms) 8-bit resolution pwm operation (conversion cycle: 102 m s to 839 ms) both 8-bit pwm timer 1 and 8-bit pwm timer 2 can output 2 channels. mb89653ar part number parameter
3 mb89650ar series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) in the case of the mb89pv650a, the voltage varies with the restrictions of the eprom for use. n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. mb89655ar mb89656ar mb89657ar mb89p657a mb89pv650a 8-bit serial i/o 8 bits lsb first/msb first selectability one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) 8-bit a/d converter 8-bit resolution 8 channels a/d conversion mode (conversion time: 18 m s) sense mode (conversion time: 5 m s) continuous activation by an internal timer capable reference voltage input external interrupt 1 4 independent channels (edge selection) rising edge/falling edge selectability used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) external interrupt 2 (wake-up function) l level interrupt 12 channels standby mode subclock mode, sleep mode, watch mode, and stop mode process cmos operating voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use ? mbm27c256a- 20tvm package mb89653ar mb89655ar mb89656ar mb89657ar mb89p657a mb89pv650a fpt-100p-m05 fpt-100p-m06 mqp-100c-p02 mb89653ar part number parameter
4 mb89650ar series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89653ar, the upper half of the register bank cannot be used. ? on the mb89p657a, the program area starts from address 8006 h but on the mb89pv650a and mb89657ar starts from 8000 h . (on the mb89p657a, addresses 8000 h to 8005 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv650a and mb89657a, addresses 8000 h to 8005 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p657a.) ? the stack area, etc., is set at the upper limit of the ram. 2. current consumption ? in the case of the mb89pv650a, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-up resistor cannot be set for p70 to p75 on the mb89p657a. on this product, a pull-up resistor must be selected in a group of four bits for p14 to p17, p40 to p43, and p44 to p47. ? a pull-up resistor is not selectable for p30 to p37 and p40 to p47 if they are used as lcd pins. ? options are fixed on the mb89pv650a. 4. differences between the mb89650a and mb89650ar series ? electrical specifications/electrical characteristics electrical specifications of the mb89650ar series are the same with that of the mb89650a series. electrical characteristics of both series are much the same. ? oscillation circuit type in the mb89650a series, the circuit type of using an external clock differs from that of using a crystal or ceramic resonator as follows. circuit type of the mb89650ar series is a circuit type in using external clock even when crystal or ceramic resonator is selected. ? memory access area and other specifications of both the mb89650a and mb89650ar series are the same.
5 mb89650ar series ? i/o circuit type n correspondence between the mb89650a and mb89650ar series ? the mb89650ar series is the reduction version of the mb89650a series. ? the mb89650a and mb89650ar series consist of the following products: type circuit remarks a ? crystal or ceramic oscillation type (main clock) mb89pv650a and mb89p657a, external clock input selection versions of mb89653a/655a/656a/657a at an oscillation feedback resistor of approximately 1 m w /5.0 v ? crystal or ceramic oscillation type (main clock) crystal or ceramic oscillation selection versions of mb89653a/655a/656a/657a at an oscillation feedback resistor of approximately 1 m w /5.0 v mb89650a series mb89653a mb89655a mb89656a mb89657a mb89p657 a mb89pv650 a mb89650ar series mb89653a r mb89655a r mb89656a r mb89657a r x1 x0 standby control signal x1 x0 standby control signal
6 mb89650ar series n pin assignment (fpt-100p-m05) (top view) 1 mod0 p52/pwm21 75 mod1 p51/pwm12 x0 p50/pwm11 x1 com3/p81 5 v ss com2/p80 rst com1 70 p00/int20 com0 p01/int21 v0 p02/int22 v1 10 p03/int23 v2 p04/int24 v3 65 p05/int25 p83 p06/int26 p82 p07/int27 seg00 15 p10/int10 seg01 p11/int11 seg02 60 p12/int12 seg03 p13/int13 seg04 p14/int28 seg05 20 p15/int29 v ss p16/int2a seg06 55 p17/int2b seg07 p20 seg08 p21 seg09 25 p22 seg10 51 26 p24/si x0a 100 p25/so x1a p26/sck v cc p30/seg31 p75 30 p31/seg30 p74 p32/seg29 p73 95 p33/seg28 p72/buz p34/seg27 p71/ec2 p35/seg26 p70/ec1 35 p36/seg25 avr p37/seg24 av cc 90 p40/seg23 p67/an7 p41/seg22 p66/an6 p42/seg21 p65/an5 40 p43/seg20 p64/an4 p44/seg19 p63/an3 85 p45/seg18 p62/an2 p46/seg17 p61/an1 p47/seg16 p60/an0 45 seg15 av ss seg14 p57/to22 80 v cc p56/to21/hclk seg13 p55/to12 seg12 p54/to11/lclk 50 seg11 p53/pwm22 76 2 3 4 6 7 8 9 11 12 13 14 16 17 18 19 21 22 23 24 27 28 29 31 32 33 34 36 37 38 39 41 42 43 44 46 47 48 49 54 53 52 59 58 57 56 64 63 62 61 66 67 68 69 74 73 72 71 77 78 79 81 82 83 84 86 87 88 89 91 92 93 94 96 97 98 99
7 mb89650ar series (fpt-100p-m06) (top view) 1 v cc p54/to11/lclk 80 2 x1a p53/pwm22 79 3 x0a p52/pwm21 78 4 mod0 p51/pwm12 77 5 mod1 p50/pwm11 76 6 x0 com3/p81 75 7 x1 com2/p80 74 8 v ss com1 73 9 rst com0 72 10 p00/int20 v0 71 11 p01/int21 v1 70 12 p02/int22 v2 69 13 p03/int23 v3 68 14 p04/int24 p83 67 15 p05/int25 p82 66 16 p06/int26 seg00 65 17 p07/int27 seg01 64 18 p10/int10 seg02 63 19 p11/int11 seg03 62 20 p12/int12 seg04 61 21 p13/int13 seg05 60 22 p14/int28 v ss 59 23 p15/int29 seg06 58 24 p16/int2a seg07 57 25 p17/int2b seg08 56 26 p20 seg09 55 27 p21 seg10 54 28 p22 seg11 53 29 p24/si seg12 52 30 p25/so seg13 51 31 p26/sck 32 p30/seg31 33 p31/seg30 34 p32/seg29 35 p33/seg28 36 p34/seg27 37 p35/seg26 38 p36/seg25 39 p37/seg24 40 p40/seg23 41 p41/seg22 42 p42/seg21 43 p43/seg20 44 p44/seg19 45 p45/seg18 46 p46/seg17 47 p47/seg16 48 seg15 49 seg14 50 v cc p75 100 p74 99 p73 98 p72/buz 97 p71/ec2 96 p70/ec1 95 avr 94 av cc 93 p67/an7 92 p66/an6 91 p65/an5 90 p64/an4 89 p63/an3 88 p62/an2 87 p61/an1 86 p60/an0 85 av ss 84 p57/to22 83 p56/to21/hclk 82 p55/to12 81
8 mb89650ar series ? pin assignment on package top (mb89pv650a only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 101 v pp 109 n.c. 117 o4 125 oe 102 a12 110 a2 118 o5 126 n.c. 103a7111a1119o6127a11 104a6112a0120o7128a9 105a5113o1121o8129a8 106a4114o2122ce 130 a13 107 a3 115 o3 123 a10 131 a14 108 n.c. 116 v ss 124 n.c. 132 v cc (top view) mod0 mod1 x0 x1 v ss rst p00/int20 p01/int21 p02/int22 p03/int23 p04/int24 p05/int25 p06/int26 p07/int27 p10/int10 p11/int11 p12/int12 p13/int13 p14/int28 p15/int29 p16/int2a p17/int2b p20 p21 p22 p52/pwm21 p51/pwm12 p50/pwm11 com3/p81 com2/p80 com1 com0 v0 v1 v2 v3 p83 p82 seg00 seg01 seg02 seg03 seg04 seg05 v ss seg06 seg07 seg08 seg09 seg10 x0a x1a v cc p75 p74 p73 p72/buz p71/ec2 p70/ec1 avr av cc p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 av ss p57/to22 p56/to21/hclk p55/to12 p54/to11/lclk (mqp-100c-p02) p24/si p25/so p26/sck p30/seg31 p31/seg30 p32/seg29 p33/seg28 p34/seg27 p35/seg26 p36/seg25 p37/seg24 p40/seg23 p41/seg22 p42/seg21 p43/seg20 p44/seg19 p45/seg18 p46/seg17 p47/seg16 seg15 seg14 v cc seg13 seg12 seg11 p53/pwm22 112 a0 111 a1 110 a2 109 n.c. 108 n.c. 107 a3 106 a4 105 a5 o8 ce a10 n.c. oe n.c. a11 a9 121 122 123 124 125 126 127 128 120 o7 119 o6 118 o5 117 o4 116 v ss 115 o3 114 o2 113 o1 a8 a13 a14 v cc v pp a12 a7 a6 129 130 131 132 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 99 100 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
9 mb89650ar series n pin description (continued) *1: fpt-100p-m06 *2: fpt-100p-m05 *3: mqp-100c-p02 pin no. pin name circuit type function qfp *1 mqfp *2 sqfp *3 41mod0 j operating mode selection pins connect to v ss (gnd) when using. 52mod1 6 3 x0 a main clock crystal oscillator pins (max. 10 mhz) 74x1 85v ss ? power supply (gnd) pin 96rst j reset input pin 10 to 17 7 to 14 p00/int20 to p07/int27 f general-purpose i/o ports also serve as an external interrupt 2 input (wake-up function). external interrupt 2 input (int20 to int27 ) is hysteresis input while port input (p00 to p07) is cmos input. 18 to 21 15 to 18 p10/int10 to p13/int13 f general-purpose i/o ports also serve as an external interrupt 1 input. external interrupt 1 input (int10 to int13) is hysteresis input while port input (p10 to p13) is cmos input. 22 to 25 19 to 22 p14/int28 to p15/int2b f general-purpose i/o ports also serve as an external interrupt 2 input (wake-up function). external interrupt 2 input (int28 to int2b ) is hysteresis input while port input (p14 to p17) is cmos input. 26 to 28 23 to 25 p20 to p22 c general-purpose i/o ports 29, 30, 31 26, 27, 28 p24/si, p25/so, p26/sck f general-purpose i/o ports the output type can be switched between n-ch open- drain and cmos. these ports also serve as an 8-bit serial i/o. the p26/sck pin is a cmos input type when it functions as the port input (p26) while the pin is a hysteresis input type when it functions as the serial clock input (sck). 32 to 47 29 to 44 p36/seg31 to p47/seg26 h general-purpose i/o ports also serve as an lcd controller/driver segment output. 48, 49 45, 46 seg15, seg14 i lcd controller/driver segment output pins
10 mb89650ar series (continued) *1: fpt-100p-m06 *2: fpt-100p-m05 *3: mqp-100c-p02 pin no. pin name circuit type function qfp *1 mqfp *2 sqfp *3 50 47 v cc ? power supply pin 51 to 58 48 to 55 seg13 to seg06 i lcd controller/driver segment output pins 59 56 v ss ? power supply (gnd) pin 60 to 65 57 to 62 seg05 to seg00 i lcd controller/driver segment output pins 66, 67 63, 64 p82, p83 c general-purpose i/o ports 68 to 71 65 to 68 v3 to v0 ? lcd driving power supply pins 72, 73 69, 70 com0, com1 i lcd controller/driver common output pins 74, 75 71, 72 com2/p80, com3/p81 h general-purpose i/o ports also serve as an lcd controller/driver common output. 76 to 79 73 to 76 p50/pwm11 to p53/pwm22 g general-purpose output ports also serve as an 8-bit pwm timer. 80, 81, 82, 83 77, 78, 79, 80 p54/to11/lclk, p55/to12, p56/to21/hclk, p57/to22 g general-purpose output ports also serve as an 8/16-bit timer. p54 and p56 also serve as a 32.768 khz oscillation output/10 mhz divide-by-two output. 84 81 av ss ? a/d converter power supply (gnd) pin 85 to 92 82 to 89 p60/an0 to p67/an7 e general-purpose input ports also serve as an analog input. 93 90 av cc ? a/d converter power supply pin 94 91 avr ? a/d converter reference voltage input pin 95, 96 92, 93 p70/ec1, p71/ec2 k general-purpose n-ch open-drain i/o ports also serve as an 8/16-bit timer to input hysteresis. 97, 98 to 100 94, 95 to 97 p72/buz, p73 to p75 d general-purpose n-ch open-drain i/o ports p72 also serves as a buzzer output. 198v cc ? power supply pin 2 99 x1a b subclock crystal oscillator pins (32.768 khz) 3100x0a
11 mb89650ar series ? external eprom pins (mb89pv650a only) pin no. pin name i/o function 101 v pp o h level output pin 102 103 104 105 106 107 110 111 112 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 113 114 115 o1 o2 o3 i data input pins 116 v ss o power supply (gnd) pin 117 118 119 120 121 o4 o5 o6 o7 o8 i data input pins 122 ce o rom chip enable pin outputs h during standby. 123 a10 o address output pin 125 oe o rom output enable pin outputs l at all times. 127 128 129 a11 a9 a8 o address output pins 130 a13 o address output pin 131 a14 o address output pin 132 v cc o eprom power supply pin 108 109 124 126 n.c. internally connected pins be sure to leave them open.
12 mb89650ar series n i/o circuit type (continued) type circuit remarks a ? crystal or ceramic oscillation type (main clock) mb89pv650a and mb89p657a, external clock input selection versions of mb89653ar/655ar/656ar/ 657ar at an oscillation feedback resistor of approximately 1 m w /5.0 v b ? crystal or ceramic oscillation type (subclock) mb89pv650a, mb89p657a at an oscillation feedback resistor of approximately 4.5 m w /5.0 v ? crystal or ceramic oscillation type (subclock) mb89653ar/655ar/656ar/657ar at an oscillation feedback resistor of approximately 4.5 m w /5.0 v c ? cmos i/o ? pull-up resistor optional (except p82 and p83) d ? n-ch open-drain i/o ? cmos input ? pull-up resistor optional e ? a/d converter input ? cmos input ? pull-up resistor optional x1 x0 standby control signal x1a x0a standby control signal x1a x0a standby control signal p-ch r n-ch p-ch r n-ch p-ch ain r n-ch p-ch
13 mb89650ar series (continued) type circuit remarks f ? cmos i/o (when selected as general-purpose ports) p24 to p26 outputs can be switched between cmos and n-ch open-drain. ? when toggled as hysteresis input peripherals. however, si input excluded. ? pull-up resistor optional g ? cmos output h ? lcd controller/driver output ?cmos i/o ? pull-up resistor optional i ? lcd controller/driver output j k ? hysteresis input ? n-ch open-drain output ? pull-up resistor optional n-ch p-ch p-ch r n-ch p-ch p-ch n-ch r p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch n-ch p-ch r
14 mb89650ar series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
15 mb89650ar series n programming to the eprom on the mb89p657a the mb89p657a is an otprom version of the mb89650a series. 1. features ? 32-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 32-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the mb89p657a functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 32 kbytes (8006 h to ffff h ) the prom can be programmed as follows: ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0006 h to 7fff h (note that addresses 8006 h to ffff h while operating as a single chip assign to 0006 h to 7fff h in eprom mode). load option data into addresses 0000 h to 0005 h of the eprom programmer. (for information about each corresponding option, see 7. setting otprom options.) (3) program to 0000 h to 7fff h with the eprom programmer. prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip i/o ram 8006 h not available 7fff h 0000 h 0006 h eprom 32 kb option area (corresponding addresses on the eprom programmer) address eprom mode
16 mb89650ar series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 note: connect the rom-100sqf-28dp-8l jumper pin to v ss when using. depending on the eprom programmer, inserting a capacitor of about 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. package compatible socket adapter fpt-100p-m05 rom-100sqf-28dp-8l fpt-100p-m06 rom-100qf-28dp-8l2 program, verify aging +150?, 48 hrs. data verification assembly
17 mb89650ar series 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map notes: set each bit to 1 to erase. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable p81 pull-up 1: no 0: yes p80 pull-up 1: no 0: yes single/dual- clock system 1: dual clock 2: single clock 0001 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0002 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0003 h p67 pull-up 1: no 0: yes p66 pull-up 1: no 0: yes p65 pull-up 1: no 0: yes p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes 0004 h p47 to p44 pull-up 1: no 0: yes p43 to p40 pull-up 1: no 0: yes p26 pull-up 1: no 0: yes p25 pull-up 1: no 0: yes p24 pull-up 1: no 0: yes p22 pull-up 1: no 0: yes p21 pull-up 1: no 0: yes p20 pull-up 1: no 0: yes 0005 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p17 to p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes
18 mb89650ar series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tvm 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel 81-3-3802-5760 3. memory space memory space in each mode, such as 32-kbyte prom, option area is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0006 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32(rectangle) rom-32lc-28dp-yg lcc-32(square) rom-32lc-28dp-s prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip i/o ram 8006 h not available 7fff h 0000 h 0006 h eprom 32 kb option area corresponding addresses on the eprom programmer address
19 mb89650ar series n block diagram x0 x1 time-base timer clock controller 2 i/o port v0 to v3 ram f 2 mc-8l cpu rom mod 2, v cc 2 v ss 2 av cc , av ss , avr other pins 8-bit timer/ counter 1 buzzer output external interrupt 2 (wake-up function) 8 8 input port p60/an0 to p67/an7 8 8 p00/int20 to p07/int27 p70/ec1 p54/to11 /lclk p55/to12 p71/ec2 p57/to22 i/o port 8-bit a/d converter external interrupt 1 4 4 p10/int10 to p13/int13 3 p20 to p22 4 4 p14/int28 to p17/int2b 8-bit serial i/o p26/sck p25/so p24/si p73 to p75 p72/buz 8-bit timer/ counter 2 8-bit timer/ counter 3 p56/to21 /hclk 8-bit timer/ counter 4 8-bit pwm timer 2 8-bit pwm timer 1 p53/pwm22 p52/pwm21 p51/pwm12 p50/pwm11 output port lcd display ram (16 8 bits) 4 2 2 2 16 8 32 8 com2/p80, com3/p81 com0, com1 seg00 to seg15 p40/seg23 to p47/seg16 p30/seg31 to p37/seg24 x0a x1a subclock oscillator (32.768 khz) main clock oscillator rst internal bus reset circuit lcd controller/driver 3 p82, p83 2
20 mb89650ar series n cpu core 1. memory space the microcontrollers of the mb89650ar series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89650ar series is structured as illustrated below. memory space *: this is an internal prom on the mb89p657a. since addresses 8000 h to 8005 h for the mb89p657a comprise an option area, do not use this area for the mb89pv650a. 0000 h 0080 h 0100 h 0480 h 8006 h i/o ram 1 kb register not available external rom* 32 kb 0000 h 0080 h 0180 h e000 h ffff h 0000 h 0080 h 01ff h 0280 h c000 h ffff h 0000 h 0080 h 01ff h 0380 h a000 h 0000 h 0080 h 0100 h 0480 h ffff h rom 8 kb mb89653ar mb89pv650a mb89p657a 01ff h i/o ram 256 b i/o ram 512 b mb89655ar register 0100 h not available not available i/o ram 768 b mb89656ar not available register register 0100 h 0100 h register 01ff h i/o ram 1 kb mb89657ar not available 8006 h ffff h ffff h rom 16 kb rom 24 kb rom 32 kb
21 mb89650ar series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 other bits are undefined. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
22 mb89650ar series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is allowed when this flag is set to 1. interrupt is prohibited when the flag is set to 0. set to 0 when reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set if the msb is set to 1 as the result of an arithmetic operation. cleared when the bit is set to 0. z-flag: set when an arithmetic operation results in 0. cleared otherwise. v-flag: set if the complement on 2 overflows as a result of an arithmetic operation. reset if the overflow does not occur. c-flag: set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
23 mb89650ar series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 16 banks can be used on the mb89653ar (ram 256 8 bits). the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. up to a total of 32 banks can be used on other than the mb89653ar. register bank configuration this address = 0100 h + 8 (rp) memory area 16 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
24 mb89650ar series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (r/w) ddr2 port 2 data direction register 06 h vacancy 07 h (r/w) scc system clock control register 08 h (r/w) smc system mode control register 09 h (r/w) wdtc watchdog time control register 0a h (r/w) tbtc time-base timer control register 0b h (r/w) wcr watch prescaler control register 0c h (r/w) pdr3 port 3 data register 0d h (r/w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (r/w) ddr4 port 4 data direction register 10 h (r/w) t4cr timer 4 control register 11 h (r/w) t3cr timer 3 control register 12 h (r/w) t4dr timer 4 data register 13 h (r/w) t3dr timer 3 data register 14 h vacancy 15 h vacancy 16 h (r/w) pdr5 port 5 data register 17 h vacancy 18 h vacancy 19 h vacancy 1a h (w) icr6 port 6 input control register 1b h (r) pdr6 port 6 data register 1c h (r/w) pdr7 port 7 data register 1d h (r/w) chg2 port 2 switching register 1e h (r/w) cntr1 pwm 0/1 control register 1f h (w) comp1 pwm 0/1 compare register
25 mb89650ar series (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) cntr2 pwm 2/3 control register 21 h (w) comp2 pwm 2/3 compare register 22 h vacancy 23 h vacancy 24 h (r/w) t2cr timer 2 control register 25 h (r/w) t1cr timer 1 control register 26 h (r/w) t2dr timer 2 data register 27 h (r/w) t1dr timer 1 data register 28 h (r/w) smr serial mode register 29 h (r/w) sdr serial data register 2a h vacancy 2b h vacancy 2c h vacancy 2d h (r/w) adc1 a/d converter control register 1 2e h (r/w) adc2 a/d converter control register 2 2f h (r/w) adcd a/d converter data register 30 h (r/w) eie1 external interrupt 1 enable register 31 h (r/w) eif1 external interrupt 1 flag register 32 h (r/w) eie2 external interrupt 2 enable register 33 h (r/w) eif2 external interrupt 2 flag register 34 h to 5f h vacancy 60 h to 6f h (r/w) vram display data ram 70 h (r/w) lcr1 lcd controller/driver control register 1 71 h (r/w) lcr2 lcd controller/driver control register 2 72 h (r/w) pdr8 port 8 data register 73 h (w) ddr8 port 8 data direction register 74 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
26 mb89650ar series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: use av cc and v cc set at the same voltage. take care so that avr does not exceed av cc + 0.3 v and av cc does not exceed v cc , such as when power is turned on. *2: v i and v o must not exceed v cc + 0.3 v. precautions: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v *1 a/d converter reference input voltage avr v ss C 0.3 v ss + 7.0 v lcd power supply voltage v0 to v3 v ss C 0.3 v ss + 7.0 v v0 to v3 must not exceed v cc . input voltage v i v ss C 0.3 v cc + 0.3 v except p70 to p75* 2 v i2 v ss C 0.3 v ss + 7.0 v p70 to p75 output voltage v o v ss C 0.3 v cc + 0.3 v except p70 to p75* 2 v o2 v ss C 0.3 v ss + 7.0 v p70 to p75 l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
27 mb89650ar series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. figure 1 operating voltage vs. main clock operating frequency figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* mb89653ar/655ar/656ar/657ar 2.7* 6.0* v normal operation assurance range* mb89pv650a/p657a 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v lcd power supply voltage v0 to v3 v ss v cc v lcd power supply range (the optimum value is dependent on the lcd element in use.) operating temperature t a C40 +85 c 1 2 3 4 5 6 1.0 10.0 operation assurance range operating voltage (v) 5.0 main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) note: the shaded area is assured only for the mb89653a/655a/656a/657a. 2.0 3.0 4.0 6.0 7.0 8.0 9.0 analog accuracy assured in the av cc = 3.5 v to 6.0 v range 4.0 0.8 2.0 0.4 minimum execution time (instruction cycle) (ms)
28 mb89650ar series 3. dc characteristics (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter sym- bol pin condition value unit remarks min. typ. max. h level input voltage v ih1 p20 to p26, p30 to p37, p40 to p47, p60 to p67, p80 to p83 ? 0.7 v cc ? v cc + 0.3 v v ih2 p72 to p75 ? 0.7 v cc ? v ss + 6.0 v without pull- up resistor v ihs p00 to p07, p10 to p17, rst , mod0, mod1, p26 (at sc input) ? 0.8 v cc ? v cc + 0.3 v v ihs2 p70, p71 ? 0.8 v cc ? v ss + 6.0 v without pull- up resistor l level input voltage v il p20 to p26, p30 to p37, p40 to p47, p60 to p67, p72 to p75, p80 to p83 ? v ss - 0.3 ? 0.3 v cc v v is p00 to p07, p10 to p17, p26 (at sc input), p70, p71, rst , mod0, mod1 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d v ss - 0.3 ? v ss + 0.3 v n-ch open- drain v d2 ? v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p20 to p26, p30 to p37, p40 to p47, p50 to p57, p80 to p83 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol p00 to p07, p10 to p17, p20 to p26, p30 to p37, p40 to p47, p50 to p57, p70 to p75, p80 to p83 i ol = 4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li p00 to p07, p10 to p17, p20 to p26, p30 to p37, p40 to p47, p60 to p67, p70 to p75, p80 to p83, mod0, mod1, rst 0.0 v < v i < v cc ?? 5 m a without pull- up resistor pull-up resistance r pull p00 to p07, p10 to p17, p20 to p26, p30 to p37, p40 to p47, p60 to p67, p70 to p75, p80 to p81 v i = 0.0 v 25 50 100 k w with pull-up resistor p24 to p26 p70 to p75
29 mb89650ar series (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter sym- bol pin condition value unit remarks min. typ. max. power supply current *1 i cc1 v cc f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 1220ma i cc2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1.0 2ma mb89653ar/ 655ar/656ar/ 657ar/pv650a 1.52.5ma mb89p657a i ccs1 f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 3 7ma i ccs2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 0.51.5ma i ccl f cl = 32.768 khz, v cc = 3.0 v subclock mode 50100 m a mb89p657a/ 655ar/656ar/ 657ar/pv650a 500700 m a mb89p657a i ccls f cl = 32.768 khz, v cc = 3.0 v subclock sleep mode 1550 m a i cct f cl = 32.768 khz, v cc = 3.0 v ? watch mode ? main clock stop mode at dual- clock system 315 m a i cch t a = +25 c ? subclock stop mode ? main clock stop mode at single- clock system 1 m a i a av cc f ch = 10 mhz, when a/d conversion is activated 1.5 3ma i ah f ch = 10 mhz, t a = +25 c, when a/d conversion is stopped 1 m a sleep mode
30 mb89650ar series (continued) (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the power supply current is measured at the external clock. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. note: for pins which serve as the lcd and ports (p30 to p37, p40 to p47, and p80 to p81), see the port parameter when these pins are used as ports and the lcd parameter when they are used as lcd pins. parameter sym- bol pin condition value unit remarks min. typ. max. lcd divided resistance r lcd ? between v cc and v0 at v cc = 5.0 v 300 500 750 k w com0 to 3 output impedance r vcom com0 to 3 v1 to v3 = 5.0 v ? 2.5 k w seg0 to 31 output impedance r vseg seg0 to 31 ? 15 k w lcd controller/ driver leakage current i lcdl v0 to v3, com0 to 3, seg0 to seg31 ? ? 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 ? pf
31 mb89650ar series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
32 mb89650ar series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin condition value unit remarks min. typ. max. clock frequency f ch x0, x1 110mhz f cl x0a, x1a 32.768 khz clock cycle time t hcyl x0, x1 100 1000 ns t lcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 20 ns external clock p wlh p wll x0a 15.2 m s external clock input clock rising/ falling time t cr t cf x0 10 ns external clock
33 mb89650ar series 0.2 v cc x0 0.2 v cc x0 x1 t hcyl when a crystal or ceramic resonator is used x0 x1 when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf p wl p wh x0 and x1 timing and conditions main clock conditions 0.2 v cc x0a 0.2 v cc x0a x1a when a crystal or ceramic resonator is used x0a x1a when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf t lcyl p wll p wlh x0a and x1a timing and conditions subclock conditions
34 mb89650ar series (4) instruction cycle note: when operating at 10 mhz, the cycle varies with the set execution time. (5) serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s (4/f ch ) t inst = 0.4 m s when operating at f ch = 10 mhz 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz parameter symbol pin condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s t scyc t slov t shix t ivsh sck 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc so si t slsh t slov t shix t ivsh sck 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc so si 0.2 v cc t shsl 0.8 v cc internal shift clock mode external shift clock mode
35 mb89650ar series (6) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin value unit remarks min. max. peripheral input h pulse width 1 t ilih1 int10 to int13, ec1, ec2 1 t inst * m s peripheral input l pulse width 1 t ihil1 1 t inst * m s peripheral input h pulse width 2 t ilih2 int20 to int2b 2 t inst * m s peripheral input l pulse width 2 t ihil2 2 t inst * m s 0.2 v cc 0.8 v cc t ihil1 int10 to int13, ec1, ec2 0.2 v cc t ilih1 int20 to int2b 0.8 v cc 0.2 v cc 0.8 v cc t ihil2 0.2 v cc t ilih2 0.8 v cc
36 mb89650ar series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. (1) a/d glossary ? resolution analog changes that are identifiable with the a/d converter. when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin condition value unit remarks min. typ. max. resolution 8bit total error avr = av cc 1.5 lsb linearity error 1.0 lsb differential linearity error 0.9 lsb zero transition voltage v ot av ss C 1.0 lsb av ss + 0.5 lsb av ss + 2.0 lsb mv full-scale transition voltage v fst avr C 3.0 lsb avr C 1.5 lsb avr mv interchannel disparity 0.5lsb a/d mode conversion time 44 t inst * m s sense mode conversion time 12 t inst * m s analog port input current i ain an0 to an7 10 m a analog input voltage 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr = 5.0v, when a/d conversion is activated 100 ?m a i rh avr = 5.0v, when a/d conversion is stopped 1 m a
37 mb89650ar series (2) precautions ? input impedance of the analog input pins the a/d converter used for the mb89650ar series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = differential linearity error = analog input actual conversion value theoretical conversion value total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error sample hold circuit analog channel selector close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. analog input pin comparator r = 6 k w . . c = 33 pf . . analog input equivalent circuit
38 mb89650ar series n example characteristics 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25 c v in vs . v cc 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t a = +25 c v in vs . v cc 0.0 1.0 v cc ?v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25 c v cc v oh vs . i oh 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) 0.0 t a = +25 c v ol vs . i ol (1) l level output voltage (2) h level output voltage (3) h level input voltage/l level input (4) h level input voltage/l level input voltage (cmos input) voltage (hysteresis input) v ihs : threshold when input voltage in hysteresis v ils : threshold when input voltage in hysteresis characteristics is set to h level characteristics is set to l level
39 mb89650ar series (continued) i cc (ma) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2 4 6 8 10 12 14 16 divide by 8 divide by 16 divide by 64 (i cc2 ) t a = +25 c f ch = 10 mhz i cc1 vs . v cc , i cc2 vs . v cc divide by 4 (i cc1 ) i ccs (ma) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a = +25 c f ch = 10 mhz i ccs1 vs . v cc , i ccs2 vs . v cc divide by 4 (i ccs1 ) divide by 8 divide by 16 divide by 64 (i ccs2 ) i ccl ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 20 40 60 80 100 120 140 160 180 200 t a = +25 c i ccl vs . v cc i ccls ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 5 10 15 20 25 30 35 40 45 50 t a = +25 c i ccls vs . v cc (5) power supply current (external clock)
40 mb89650ar series (continued) i cct ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2 4 6 8 10 12 14 16 18 20 t a = +25 c i cct vs . v cc i cch ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 t a = +25 c i cch vs . v cc i a ( m a) av cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 i a vs . av cc t a = +25 c f ch = 10 mhz i r ( m a) avr (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 20 40 60 80 100 120 140 160 180 200 t a = +25 c i r vs . avr 234 5 6 r pull (k w ) 10 1 100 1000 v cc (v) t a = +25 c r pull vs . v cc (6) pull-up resistance
41 mb89650ar series n instructions execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
42 mb89650ar series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: number of instructions #: number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah immediately before the instruction is executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
43 mb89650ar series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
44 mb89650ar series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
45 mb89650ar series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
46 mb89650ar series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
47 mb89650ar series n mask options *1: the value at f ch = 10 mhz *2: on microcontrollers with a built-in booster, only 1/3 bias can be used. the 1/2 duty cannot be used. note: reset is input asynchronized with the internal clock whether with or without power-on reset. no. part number mb89653ar mb89655ar mb89656ar mb89657ar mb89p657a mb89pv650a specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p20 to p22, p24 to p26, p30 to p37, p40 to p47, p60 to p67, p70 to p75, p80 to p81 specify by pin can be set per pin. (select in a group of four bits for p14 to p17, p40 to p43, and p40 to p47.) (p75 to p70 are available only for without a pull-up resistor.) fixed to without pull-up resistor 2 power-on reset selection with power-on reset without power-on reset selectable with power-on reset fixed to with power-on reset 3 selection of the oscillation stabilization time initial value crystal oscillator: 2 18 /f ch (approx. 26.2 ms *1 ) ceramic oscillator: 2 13 /f ch (approx. 26.2 ms *1 ) selectable 2 18 /f c h (approx. 26.2 ms *1 ) fixed to 2 18 /f ch (approx. 26.2 ms *1 ) 4 selection either single- or dual-clock system single clock dual clock selectable setting possible fixed to dual-clock system 5 selection of a built-in booster* 2 without booster with booster (segment output switching) 16 segments:selection of p30 to p37 and p40 to p47 20 segments:selection of p30 to p37 and p40 to p43 24 segments:selection of p30 to p37 28 segments:selection of p30 to p33 32 segments:no port selection selectable can be selected from the following six options: -101: without booster -102: 16 segments -103: 20 segments -104: 24 segments -105: 28 segments -106: 32 segments fixed to without booster
48 mb89650ar series n ordering information part number package remarks mb89653apfv mb89655apfv mb89656apfv mb89657apfv mb89p657apfv-101 MB89P657APFV-102 mb89p657apfv-103 mb89p657apfv-104 mb89p657apfv-105 mb89p657apfv-106 100-pin plastic sqfp (fpt-100p-m05) mb89653apf mb89655apf mb89656apf mb89657apf mb89p657apf-101 mb89p657apf-102 mb89p657apf-103 mb89p657apf-104 mb89p657apf-105 mb89p657apf-106 100-pin plastic qfp (fpt-100p-m06) mb89pv650acf 100-pin ceramic mqfp (mqp-100c-p02)
49 mb89650ar series n package dimensions 100-pin plastic lqfp (fpt-100p-m05) dimensions in mm (inches) +0.05 C0.02 +.002 C.001 +0.20 C0.10 +.008 C.004 +0.08 C0.03 +.003 C.001 lead no. 0~10 (stand off) (.004.004) 0.100.10 0.15(.006) 0.15(.006) 0.15(.006)max 0.40(.016)max details of "a" part 0.500.20(.020.008) 76 50 51 75 100 1 26 25 "a" "b" nom (.591) ref (.472) 12.00 15.00 0.127 .005 1.50 .059 m 0.08(.003) 0.10(.004) index 0.18 .007 0.50(.0197)typ 14.000.10(.551.004)sq 16.000.20(.630.008)sq details of "b" part 1994 fujitsu limited f100007s-2c-2 c
50 mb89650ar series 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) (.031.008) 0.800.20 lead no. (.012.004) 0.300.10 0.65(.0256)typ 0.30(.012) 0.25(.010) 100 81 80 51 50 31 30 1 22.300.40(.878.016) 18.85(.742)ref m 0.13(.005) (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.35(.486) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.53(.021)max 0.10(.004) "b" "a" 1994 fujitsu limited f100008-3c-2 c
51 mb89650ar series 100-pin ceramic mqfp (mqp-100c-p02) dimensions in mm (inches) C.010 +.018 C0.25 +0.45 sq sq typ 10.92(.430) typ 0.30(.012) (.0197.0060) 0.500.15 (.007.002) 0.180.05 typ 17.20(.667) typ 12.00(.472) 17.20(.667)typ 12.00(.472)typ typ 4.50(.177)sq typ 10.92(.430) .043 1.10 9.94(.392)max (.006.002) 0.150.05 pad no.1 index typ 7.14(.281) (.040.005) 1.020.13 pin no.1 index (.591.010) 15.000.25 (.583.014) 14.820.35 1994 fujitsu limited m100002sc-2-2 c
mb89650ar series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0004 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB89P657APFV-102

	To Download MB89P657APFV-102 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .